Copyright © 2008 The Institute of Electronics, Information and Communication Engineers
Regular Section -- Papers -- Wireless Communication Technologies |
Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation
1 The authors are with the Department of Electrical and Computer Engineering, Yokohama National University, Yokohama-shi, 240-8501 Japan., 2 The author is with the Graduate School of Science and Engineering, Tokyo Institute of Technology, Tokyo, 152-8552 Japan. E-mail: mskim{at}ide.titech.ac.jp
At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.
Key Words: systolic array, QR decomposition, RLS, CORDIC, FPGA
Manuscript received March 28, 2007. Manuscript revised September 13, 2007.
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